What is MIPI?

The Mobile Industry Processor Interface (MIPI) is a high-speed data transfer protocol widely used in applications requiring transfer of large volumes of image data, such as high-resolution cameras and displays.

Thanks to its high performance, low power consumption, and minimal latency, MIPI has become a standard across multiple industries. This broad adoption has fostered a robust ecosystem, offering dedicated chips and hardware that simplify integration.

The standard is now embraced by nearly the entire mobile industry, as well as major chip vendors, automotive sectors (including ADAS and infotainment), IoT (especially wearables), AR/VR, and medical imaging—all of which rely on efficient, high-volume data transfer.

Like USB, the MIPI standard is continuously evolving, with each new version delivering higher speeds and additional features. MIPI CSI-2 stands out as the industry’s workhorse, offering up to 2.5 Gbit/s per data lane. With support for up to four lanes, it provides both high performance and flexibility.

MIPI CSI-2 creates a direct link from an image sensor (like a CMOS sensor) to an Image Signal Processor (ISP) or application processor, allowing for real-time capture and processing of visual data with minimal latency and a small physical footprint, making it essential for modern embedded vision systems.

The CSI-2 interface can be divided into three layers, namely the.

– Applications layer, where data is created, encoded and/or interpreted, like for a CMOS sensor or Image Processor.

– Transport Layer, which is responsible for data transmission, i.e. lane management, low-level protocols and pixel-to-byte conversion.

– Physical Layer, being the layer connecting the sender and receiver devices. The physical layer is typically abbreviated C-PHY for camera interface and D-PHY for display interfaces. Note that MIPI is a differential interface, meaning that all lanes (data and clock) come in pairs or a positive and negative lane.

A typical layout for the three interface layers can be seen in the image below.

The MIPI signals: Clock lanes: Sets the rate at which data is transferred over data lanes, Data lanes: Are the lanes carrying data between the transmitter and receiver.

MIPI CSI-2 operates in two modes: low-power (LP) when idle and high-speed (HS) during data transfer. The timing of transitions between these modes is determined by the specific hardware implementation.

The MIPI clock can run in either continuous or non-continuous mode. In continuous mode, the clock remains active at all times. In non-continuous mode, the clock, like the data lanes, enters a low-power state when idle, and its reactivation signals the start of a transfer.

Non-continuous clocking is more commonly used due to its power efficiency. Continuous clock mode is reserved for applications where minimal latency and maximum throughput are critical and MIPI signaling is the primary performance bottleneck.

Below is a typical example of transfer of data where the clock signal is operated in non-continuous mode. Note that both data and clock lanes are pulled low to signal the transition from low power (LP) to high speed (HS) mode.

LP-11: Both lanes are in LP mode, LP-01: One lane is LP mode and one in HS mode, LP-00: Both lanes are in HS mode.

High-speed data transfer protocols like USB3 and CameraLink are commonly used in imaging applications, each with distinct advantages and drawbacks.

CameraLink is a well-established standard for high-speed data transfer, widely adopted in spectral domain OCT systems where linear cameras traditionally use CameraLink outputs. However, it requires dedicated hardware, like frame grabber cards and PCs with compatible PCIe slots. These components can add thousands of Euro to a system’s bill of materials (BoM), significantly increasing overall costs.

USB3 (SuperSpeed) has gained popularity in recent years, largely due to the high cost of CameraLink solutions. While USB3 is more convenient and easier to implement, it generally offers lower data transfer speeds, limiting detector line rates. Additionally, USB3 demands powerful PC hardware to process the raw data output from line-scan cameras, as operating systems do not natively support these raw formats. Converting and casting data into usable types (8-bit, 16-bit, etc.) can be processor-intensive. USB3 also introduces higher latency compared to other protocols, though its ease of use keeps it a popular choice.

MIPI CSI-2 stands out by delivering both high speed and low latency at a fraction of the cost of competing technologies. Systems-on-Chip (SoCs) with integrated image signal processors (ISPs) can handle raw data directly, reducing processor load and lowering overall BoM costs. While MIPI does require hardware that supports its standard, its broad industrial adoption means many chipsets and development boards, such as Raspberry Pi (excluding Pi Zero), NVIDIA Jetson TX2, NVIDIA Nano, Qualcomm RB3, Qualcomm RB5, Arduino Spartan, and Asus Tinker Board, already offer native support. Ibsen Photonics also offer a developer kit based in the Infinion (Cypress) CX3 chip for interfacing with the M-DISB (MIPI interface) electronics board.

Although some software and hardware development are needed for specific MIPI implementations, MIPI CSI-2 provides a high-speed, cost-effective, and power-efficient platform, making it ideal for high-volume production and compact, integrated systems.